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Chapter 7 Section 7.1 62 min

Part V · Hardware foundations

Why build hardware for this computation

Connect throughput and data motion constraints to specialization.

Software schedules instructions; hardware arranges machinery

If you're coming from a software background, you're used to writing a program that hands instructions to a processor. The processor decides how to schedule and execute them. But in hardware design (specifically Register Transfer Level, or RTL), you aren't writing instructions. You're arranging the physical machinery—the registers, the arithmetic units, and the wires connecting them. That's why thinking in terms of "running the next line of code" will trip you up. In hardware, multiple pieces of logic are active simultaneously, and registers are the gatekeepers that decide which results get saved for the next clock cycle.

Look for the repetitive heavy lifting

Think about our scoring path. We're repeating the exact same modular math operations over thousands of polynomial positions, for thousands of corpus objects. It's incredibly regular, the data widths never change, and the corpus streams in steadily. That kind of predictable, high-volume repetition is exactly what custom hardware is hungry for.

Don't just count the multipliers

It's tempting to think you can just stamp out a bunch of multipliers to go faster. But a multiplier that can crunch 16 values per cycle is just going to sit there twiddling its thumbs if memory can only feed it one value at a time. On the flip side, paying for ultra-wide memory bandwidth is a waste if your math units keep stalling. Hardware is all about balancing the triangle:

compute
multipliers
movement
HBM · RAM · wires
time
cycles · latency

Worked example

Convert a stream width into a minimum bandwidth

Let's do the math. If we have 16 lanes, each eating a 28-bit residue every cycle, that's 16 × 28 = 448 payload bits per accepted beat (and that's before we even count overhead like addresses and validity flags). If we're accepting 250 million beats per second, we're asking the memory system to supply 112 gigabits per second just for that one stream. Figuring this out doesn't guarantee your design will hit that speed, but it shows you the bare minimum your memory infrastructure has to deliver.

Worked example

Why our layout choices matter to the hardware

Remember how we set up the layout so that the target coefficients already have the reductions baked in? This is where that pays off. The score engine can just stream the transformed corpus words straight through the multipliers. We don't need memory for rotation keys, we don't need complex routing networks, and we don't need a huge score-reduction tree. We used a math trick to make entire pieces of hardware disappear.

Check your understanding

Why is this scoring workload such a good fit for hardware acceleration?

Section summary

  • Specialization means trading flexibility for raw throughput.
  • You have to balance compute (multipliers), movement (memory and wires), and time (cycles).
  • Our mathematical layout choices directly simplified what we had to build in hardware.

Repository layer · second pass

What makes this workload worth specializing in hardware?

The score path repeats fixed-width modular arithmetic across many coefficients, residue limbs, and ciphertext components. Its control is regular and its parallelism is explicit. Those traits let an FPGA or ASIC trade area for throughput and keep data near arithmetic units.

Acceleration is a resource-allocation argument, not “hardware is faster.” Quantify host bandwidth, memory locality, multiplier count, clock frequency, batch occupancy, and transfer overhead. Small or irregular workloads may remain faster in optimized software.

Reasoning chain

  1. 1

    Profile the complete software path.

  2. 2

    Identify repeated stable kernels.

  3. 3

    Measure arithmetic intensity and data motion.

  4. 4

    Choose a streaming boundary.

  5. 5

    Estimate throughput and transfer overhead.

  6. 6

    Retain a software reference for correctness.

Worked trace

Offload can lose on tiny batches

  1. Device kernel saves 2 ms.
  2. Host-to-device setup costs 3 ms.
  3. One query is slower after offload.
  4. Batching 100 queries amortizes setup.

Result. Throughput and latency must be evaluated at the intended batch shape.

Executable lens · Python

Make the hidden state visible

def offload_time(batch, setup_ms=3, kernel_ms=.02):
    return setup_ms + batch * kernel_ms
def cpu_time(batch, per_ms=.05):
    return batch * per_ms

Retype this example, predict each intermediate value, and then change one input that touches a boundary.

Misconception clinic

Tempting mistakes

  • Ignoring PCIe/network transfer.
  • Assuming unlimited multipliers, RAM ports, or routing.

Retrieval and transfer

Close the book first

  1. Compute the break-even batch for the example.
  2. List resources consumed by one modular lane.
  3. Separate security boundary from acceleration boundary.