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Chapter 7 Section 7.8 80 min

Part V · Hardware foundations

Chapter studio: think in cycles

Trace waveforms, handshakes, widths, and pipeline occupancy.

Let's review the cycles

1. A producer yells 'valid!' and holds out the number 42, but the consumer keeps 'ready' at 0 for three clock ticks. What happens?

Absolutely nothing transfers. The producer has to stand there, keeping valid high and holding onto 42 until the consumer finally raises ready.

2. How wide does a wire bundle need to be to hold the full product of two 28-bit unsigned residues?

56 bits. Don't drop your data.

3. You build a four-stage pipeline that accepts a new word every cycle. What is its latency, and what is its steady-state throughput?

The latency is four cycles (the time it takes one word to get through). The steady throughput is one word per cycle (once the pipe is full).

4. How is it possible for a massive 16-lane accelerator to achieve zero throughput?

If the memory can't supply data fast enough (so valid is usually low), or the next stage is clogged up (so ready is usually low), those 16 lanes will just sit idle.

5. We're streaming a 4096-coefficient polynomial at 16 coefficients per clock cycle. How many cycles does it take if there are no stalls?

4096 / 16 = 256 accepted beats.

6. In our test module, output_valid=1 and output_ready=0. What happens on the next clock tick?

The module enters a stall. It preserves the output product, forces its own input_ready low, and refuses to accept any new inputs.

7. Why will thinking in terms of Python for loops get you in trouble when designing 16 hardware lanes?

Because a for loop executes one step at a time, sequentially. In hardware, all 16 lanes are physically built and they all execute their work simultaneously on the same clock cycle.

8. If you're documenting the contract for a hardware module's input port, what do you need to write down?

The signal widths, what the bits actually represent (signed/unsigned), the valid/ready handshake rules, what happens on a reset, and how it responds to backpressure.

HDL readiness gate

Which of these sentences proves the speaker actually understands hardware timing?

Chapter 7 complete

You're ready to read real hardware

You know that signals have physical widths. You know combinational logic takes time to ripple through gates, and registers lock in state on the clock edge. You understand how valid and ready handshakes keep data safe, how pipelines boost throughput, and how lanes give you massive parallel processing power. You have the vocabulary. Let's go look at the real production score engine.

Repository layer · second pass

Can you reason about values and time at once?

HDL mastery requires two simultaneous models: the arithmetic value produced and the cycle/handshake event that authorizes movement. A correct multiplier with misaligned valid is wrong; perfect control carrying a truncated product is also wrong.

The studio combines width proofs, waveform traces, randomized backpressure, and scoreboards. Always-ready simulation is only a smoke test. The meaningful cases fill the pipeline, stall it, release it, reset it, and cross maximum numeric bounds.

Reasoning chain

  1. 1

    Predict arithmetic reference values.

  2. 2

    Label transactions uniquely.

  3. 3

    Trace acceptance and completion edges.

  4. 4

    Inject stalls and reset boundaries.

  5. 5

    Compare outputs in accepted order.

  6. 6

    Assert no loss, duplication, reordering, or mutation.

Worked trace

A stall-safe scoreboard

  1. Push expected product only on input transfer.
  2. Pop expected product only on output transfer.
  3. During stall, compare current output with previous output.
  4. At end, require an empty expected queue.

Result. One scoreboard verifies both content and protocol accounting.

Executable lens · Python

Make the hidden state visible

expected=[]
# on input handshake: expected.append(a*b)
# on output handshake: assert data == expected.pop(0)
# while stalled: assert (valid,data) == previous
# after drain: assert not expected

Retype this example, predict each intermediate value, and then change one input that touches a boundary.

Misconception clinic

Tempting mistakes

  • Advancing expected data every cycle instead of every handshake.
  • Testing random values but deterministic always-ready control.

Retrieval and transfer

Close the book first

  1. Draw a ten-cycle adversarial waveform.
  2. Add reset mid-stream and define disposition of queued work.
  3. Explain latency, throughput, and initiation interval separately.