Read a small SystemVerilog module slowly

Okay, let's finally look at some code

SystemVerilog is a Hardware Description Language (HDL). The snippet below describes a single, buffered multiplication stage. It's deliberately simple so we can focus on the plumbing, and you can actually execute its testbench using Icarus Verilog.

module stream_multiply #(
    parameter int WIDTH = 16
) (
    input  logic                   clk,
    input  logic                   reset_n,
    input  logic                   input_valid,
    output logic                   input_ready,
    input  logic [WIDTH-1:0]       left,
    input  logic [WIDTH-1:0]       right,
    output logic                   output_valid,
    input  logic                   output_ready,
    output logic [(2*WIDTH)-1:0]   product
);
    assign input_ready = !output_valid || output_ready;

    always_ff @(posedge clk) begin
        if (!reset_n) begin
            output_valid <= 1'b0;
            product      <= '0;
        end else if (input_ready) begin
            output_valid <= input_valid;
            if (input_valid)
                product <= left * right;
        end
    end
endmodule

Start from the outside in

Look at parameter int WIDTH=16. This just makes the module configurable so we can stamp out different sizes. A line like logic [WIDTH-1:0] left is declaring a physical bundle of wires, numbered from top to bottom. Notice how the product gets 2 * WIDTH bits, to hold the full unsigned result.

Keep the two behaviors separated in your head

Look for the assign statement. This is continuous logic—it's calculating input_ready on the fly based on whether the output register is empty or about to clear out. Now look at the always_ff block. This only runs when the clock ticks. It handles the reset flag, and if the stage is ready to advance, it reaches out and grabs the new product.

Translating backpressure into a Boolean equation

This module only has room to store one output item. So, when is it allowed to accept a new input? Either when it's completely empty (!output_valid), OR when the current item is guaranteed to leave on this exact clock tick (because the downstream guy said output_ready). So, !output_valid || output_ready is just a mathematical proof of capacity compressed into a single line.

# Cycle model for the RTL stage
if reset:
    output_valid = False
elif input_ready:
    output_valid = input_valid
    if input_valid:
        output_data = a * b